Add entries for Neoverse N2,V1, and V2 into CRC dynamic dispatch table.

PiperOrigin-RevId: 571430428
Change-Id: I4777c37c5287d26a75f37fe059324ac218878f0e

absl/crc/internal/cpu_detect.cc

@@ -243,11 +243,26 @@ CpuType GetCpuType() {
     ABSL_INTERNAL_AARCH64_ID_REG_READ(MIDR_EL1, midr);
     ABSL_INTERNAL_AARCH64_ID_REG_READ(MIDR_EL1, midr);
     uint32_t implementer = (midr >> 24) & 0xff;
     uint32_t implementer = (midr >> 24) & 0xff;
     uint32_t part_number = (midr >> 4) & 0xfff;
     uint32_t part_number = (midr >> 4) & 0xfff;
-    if (implementer == 0x41 && part_number == 0xd0c) {
-      return CpuType::kArmNeoverseN1;
+    switch (implementer) {
+      case 0x41:
+        switch (part_number) {
+          case 0xd0c: return CpuType::kArmNeoverseN1;
+          case 0xd40: return CpuType::kArmNeoverseV1;
+          case 0xd49: return CpuType::kArmNeoverseN2;
+          case 0xd4f: return CpuType::kArmNeoverseV2;
+          default:
+            return CpuType::kUnknown;
         }
         }
-    if (implementer == 0xc0 && part_number == 0xac3) {
-      return CpuType::kAmpereSiryn;
+        break;
+      case 0xc0:
+        switch (part_number) {
+          case 0xac3: return CpuType::kAmpereSiryn;
+          default:
+            return CpuType::kUnknown;
+        }
+        break;
+      default:
+        return CpuType::kUnknown;
     }
     }
   }
   }
   return CpuType::kUnknown;
   return CpuType::kUnknown;

absl/crc/internal/cpu_detect.h

@@ -39,7 +39,10 @@ enum class CpuType {
   kIntelSandybridge,
   kIntelSandybridge,
   kIntelWestmere,
   kIntelWestmere,
   kArmNeoverseN1,
   kArmNeoverseN1,
+  kArmNeoverseV1,
   kAmpereSiryn,
   kAmpereSiryn,
+  kArmNeoverseN2,
+  kArmNeoverseV2
 };
 };
 
 
 // Returns the type of host CPU this code is running on.  Returns kUnknown if
 // Returns the type of host CPU this code is running on.  Returns kUnknown if

absl/crc/internal/crc_x86_arm_combined.cc

@@ -634,11 +634,16 @@ CRCImpl* TryNewCRC32AcceleratedX86ARMCombined() {
       return new CRC32AcceleratedX86ARMCombinedMultipleStreams<
       return new CRC32AcceleratedX86ARMCombinedMultipleStreams<
           3, 0, CutoffStrategy::Fold3>();
           3, 0, CutoffStrategy::Fold3>();
     case CpuType::kArmNeoverseN1:
     case CpuType::kArmNeoverseN1:
+    case CpuType::kArmNeoverseN2:
+    case CpuType::kArmNeoverseV1:
       return new CRC32AcceleratedX86ARMCombinedMultipleStreams<
       return new CRC32AcceleratedX86ARMCombinedMultipleStreams<
           1, 1, CutoffStrategy::Unroll64CRC>();
           1, 1, CutoffStrategy::Unroll64CRC>();
     case CpuType::kAmpereSiryn:
     case CpuType::kAmpereSiryn:
       return new CRC32AcceleratedX86ARMCombinedMultipleStreams<
       return new CRC32AcceleratedX86ARMCombinedMultipleStreams<
           3, 2, CutoffStrategy::Fold3>();
           3, 2, CutoffStrategy::Fold3>();
+    case CpuType::kArmNeoverseV2:
+      return new CRC32AcceleratedX86ARMCombinedMultipleStreams<
+          1, 2, CutoffStrategy::Unroll64CRC>();
 #if defined(__aarch64__)
 #if defined(__aarch64__)
     default:
     default:
       // Not all ARM processors support the needed instructions, so check here
       // Not all ARM processors support the needed instructions, so check here